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CPU memory map

$0000–$07FFInternal RAM2048 B

$0800–$1FFFRAM Mirror ×36144 B

$2000–$2007PPU Registers8 B

$2008–$3FFFPPU Mirror8184 B

$4000–$4017APU / I/O24 B

$4018–$401FAPU Test (disabled)8 B

$4020–$5FFFExpansion / Mapper8160 B

$6000–$7FFFPRG-RAM / WRAM8192 B

$8000–$BFFFPRG-ROM (low bank)16384 B

$C000–$FFF9PRG-ROM (high bank)16378 B

$FFFA–$FFFBNMI Vector2 B

$FFFC–$FFFDRESET Vector2 B

$FFFE–$FFFFIRQ / BRK Vector2 B

cpu registers quick reference

PPU Registers ($2000–$2007)

$2000PPUCTRL[W]NMI enable, master/slave, sprite height, BG/sprite tile select, VRAM addr inc, nametable base

$2001PPUMASK[W]color emphasis, sprite enable, background enable, sprite/BG left-column clip, greyscale

$2002PPUSTATUS[R]VBlank flag, sprite 0 hit, sprite overflow — read resets $2005/$2006 write latch

$2003OAMADDR[W]OAM address — set before reading/writing $2004

$2004OAMDATA[RW]OAM data — read/write one byte of Object Attribute Memory (256 bytes)

$2005PPUSCROLL[W]scroll position (write twice: X then Y)

$2006PPUADDR[W]PPU VRAM address (write twice: high byte then low byte)

$2007PPUDATA[RW]PPU VRAM data — auto-increments address by 1 or 32 (PPUCTRL bit 2)

APU / I/O Registers ($4000–$4017)

$4000SQ1_VOL[W]Pulse 1: duty, loop envelope/halt, constant volume, volume/period

$4001SQ1_SWEEP[W]Pulse 1: sweep enable, period, negate, shift

$4002SQ1_LO[W]Pulse 1: timer low 8 bits

$4003SQ1_HI[W]Pulse 1: length counter load, timer high 3 bits

$4004SQ2_VOL[W]Pulse 2: duty, loop envelope/halt, constant volume, volume/period

$4005SQ2_SWEEP[W]Pulse 2: sweep enable, period, negate, shift

$4006SQ2_LO[W]Pulse 2: timer low 8 bits

$4007SQ2_HI[W]Pulse 2: length counter load, timer high 3 bits

$4008TRI_LINEAR[W]Triangle: linear counter control/halt, counter reload value

$400ATRI_LO[W]Triangle: timer low 8 bits

$400BTRI_HI[W]Triangle: length counter load, timer high 3 bits

$400CNOISE_VOL[W]Noise: loop envelope/halt, constant volume, volume/period

$400ENOISE_LO[W]Noise: loop, noise period

$400FNOISE_HI[W]Noise: length counter load

$4010DMC_FREQ[W]DMC: IRQ enable, loop, frequency index

$4011DMC_RAW[W]DMC: direct load (7-bit)

$4012DMC_START[W]DMC: sample address = $C000 + value×64

$4013DMC_LEN[W]DMC: sample length = value×16 + 1 bytes

$4014OAM_DMA[W]Sprite DMA — write high byte of 256-byte page to copy into OAM (513–514 CPU cycles)

$4015APU_STATUS[RW]R: DMC interrupt, frame interrupt, DMC active, length counter status. W: enable/disable channels

$4016JOY1[RW]W: joypad strobe. R: Controller 1 serial data (bit 0)

$4017JOY2[RW]W: APU frame counter mode and IRQ inhibit. R: Controller 2 serial data